1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which enables the use of articles that used to be classified conventionally as defective as conforming articles without relying upon the use of a redundant circuit.
2. Description of the Prior Art
A semiconductor memory device includes a memory cell array consisting of a plurality of memory cells provided in array form and a plurality of bit lines and word lines that are respectively connected to the memory cells, and a row decoder and a column decoder that are respectively arranged adjacent to the memory cell array so as to select a specified memory cell. The plurality of bit lines in the memory cell array includes a plurality of bit line pairs, the levels of lines of each bit line pair becoming complementary with each other, and one sense amplifier is provided for each of the bit line pair. The sense amplifier is activated in response to a sense amplifier activating signal, and amplifies the potential difference between the two bit lines that constitute the bit line pair.
A selection switch selects one bit line pair in response to a selection signal from the column decoder, and electrically connects the selected bit line pair to the I/O pairs for read and write of a data to a memory cell.
In a conventional semiconductor device described as in the above, the column decoder is controlled by a delayed signal of a sense amplifier activating signal in order to realize the connection between a predetermined bit line pair and the I/O lines at the time of data read after the amplification of the potential difference of the bit line pair by means of a sense amplifier has proceeded sufficiently well. Namely, the semiconductor memory device is given a constitution in which a sense amplifier amplifying signal is delayed by a predetermined time (6 to 10 ns) by a delay circuit so as to have a selection signal generated by the column decoder after sufficiently long period of time (about 6 to 10 ns) for adequately amplifying the potential difference of the bit line pair following the activation of the sense amplifier by the sense amplifier amplifying signal, then a selection signal is generated when the delayed signal is applied to the column decoder.
Now, the function test of a semiconductor memory cell is carried out generally in the wafer state, and when a defective spot is discovered, the defective spot is corrected with a redundant bit line of a redundant word line to make it usable as a conforming article. One of the various kinds of factors for the generation of defective spots is a read error caused by the formation of electrical connection a bit line pair and the I/O lines during the period from the activation of a sense amplifier to the action of the selection switch before the sense amplifier sufficiently amplified the potential difference of the bit line pair. That is, there is a case where the potential difference of the bit line pair is small due to fluctuations of the characteristics of the transistors or the capacitor elements that constitute the memory cell selected, or a case where the performance of the sense amplifier is deteriorated due to fluctuations of the characteristics of the elements that constitute the sense amplifier. In such a case, it is not possible to raise the amplification of the potential difference of the bit line pair by the sense amplifier to a sufficiently high level during the predetermined time. If the connection between the bit line pair and the I/O lines is formed in such a state, it will not only prolong the read time but also it may lead to the generation of a read error due to reversal of the potential levels of the pair of bit lines depending upon circumstances.
Even for a read error due to the above-mentioned cause, it has been conventional to use the device as a conforming article by replacing the relevant bit line pair by redundant bit lines. However, when there are many bit line pairs that generate the read errors, it is not possible to replace all of the bit line pairs that produce the read errors, so that these has been a defect in that it results in a deterioration of the yield and a rise in the cost.